1. Field of the Invention
The present invention relates to the field of digital computer systems, and more particularly, to the programming of a direct memory access controller located on a bridge between two buses by a scatter/gather programmer.
2. Description of Related Art
In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen (16) megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus machines remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, etc. can also attach directly or indirectly (e.g., through a host bridge) to the PCI bus.
A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially translates the ISA bus cycles to PCI bus cycles, and vice versa.
Many of the devices attached to the PCI bus and the ISA bus are master devices that can conduct processing independently of the bus or other devices. Certain devices coupled to the buses are considered to be slaves or targets that accept commands and respond to requests of a master. The PCI bus has an addressing capability of 32 bits to provide for 4 gigabytes of memory access. A master on the ISA bus can access a memory location in the memory on the PCI bus, although normally only within the lowest 16 megabyte region due to the 24-bit addressing of the ISA bus masters.
In a digital computer, a microprocessor operates on data stored in a main memory. Since there are practical size limitations on the main memory, bulk memory storage devices are provided in addition to and separately from the main memory. When the microprocessor wants to make use of data stored in bulk storage, for example, a hard disk, the data is moved from the hard disk into the main memory. This movement of blocks of memory inside the computer is a very time consuming process and would severely hamper the performance of the computer system if the microprocessor were to control the memory transfers itself.
In order to relieve the microprocessor from the chore of controlling the movement of blocks of memory inside the computer, a direct memory access (DMA) controller is normally used. The DMA controller receives information from the microprocessor as to the base location from where bytes are to be moved, the address to where these bytes should go, and the number of bytes to move. Once it has been programmed by the microprocessor, the DMA controller oversees the transfer of the memory data within the computer system. Normally, DMA operations are used to move data between input/output (I/O) devices and memory.
The programming of a DMA controller by a central processing unit (CPU) requires the intervention of the processor for a relatively long time, since program input/output (I/O) cycles are run with standard ISA cycles. The processor cannot run other programs when it is programming the DMA controller. To improve system efficiency, scatter/gather units have been developed which take over from the CPU the programming of the DMA controller.
A scatter/gather unit essentially fetches descriptors, which are small blocks of memory, and programs these descriptors into the DMA controller. A descriptor includes a DMA address, a transfer count, and an end of link bit. The DMA address indicates the address where the data will be sent to or retrieved from; the transfer count indicates how large a block of data will be transferred; and the end of link bit indicates whether or not chaining is being used. When chaining is used, so that the end of link bit is cleared, the scatter/gather unit recognizes that there is another descriptor with a subsequent eight bytes (contiguous addressing), which contains another scatter/gather transfer.
In operation, therefore, the CPU will program a scatter/gather descriptor table in memory, which requires much less time than writing to slow I/O devices. The CPU then sends an instruction to the DMA controller to instruct it to prepare to perform a transfer, and an instruction to the scatter/gather unit to begin the transfer. The CPU's role is complete at this point and the scatter/gather unit retrieves the descriptor information from memory and programs the DMA controller with the information. The DMA controller is activated and operates as usual. The DMA controller is not aware that it was programmed by a scatter/gather unit and not the CPU with slow I/O accesses.
The "scatter" operation is a DMA transfer from I/O to memory, so that data is being read from a peripheral I/O device or a floppy disk, etc., and is scattered into memory. In a "gather" operation, the DMA controller is programmed to read memory and write to I/O by gathering different non-contiguous segments of memory and then writing them to I/O in a continuous manner.
A known bridge chip used to bridge an ISA bus and a PCI bus that contains a scatter/gather unit is available from Intel Corporation. When programming the DMA controller that is also located on the bridge chip, the scatter/gather unit runs ISA bus cycles on the ISA bus. These bus cycles are I/O cycles that are run on a bus that operates at 8 MHz. In comparison to the 33 MHz speed of the PCI bus, the 8 MHz bus is extremely slow, so that the programming of the DMA controller by the scatter/gather unit in the known device is also extremely slow.